(1) Field of the Invention
The present invention relates in general to high density electronic devices, more particularly to a device structure that embodies a three dimensional multichip array interconnected and supported on a base semiconductor device substrate, and methods of fabricating.
(2) Description of the Related Art
Since the development of integrated circuit technology, semiconductor devices have been made from monocrystalline semiconductor materials, i.e. silicon, that has been crystallized from molten silicon into a single crystal boule. The boule is sliced into wafers, the wafers polished, and semiconductor elements formed and interconnected with metallurgy stripes. The wafers are divided into devices, which are electrically bonded to carriers of various types. Electrical connections are made to the devices by either, solder bumps, aluminum ultrasonic bonding, gold bumps, thermal compressions bonded wires, decals, etc. As the devices become more microminiaturized, the electrical connections become more difficult, and the yield has decreased. When the size of the devices were made larger and the number of active and passive elements was increased, the yield decreased since there were more possibilities for defects in a single device. Further, long lines prevented effective power input and frequently produced undesirable signal delays.
Efforts to overcome these problems led to connecting IC (Integrated Circuit) devices directly to each other, instead of each device to a support package, and connecting the support package. U.S. Pat. No. 4,807,021 and U.S. Pat. No. 5,202,754 are illustrative of such efforts. However, the fabrication of such multiple device packages proved to be difficult, painstaking, and expensive. U.S. Pat. No. 5,191,405 discloses a variation consisting of a three-dimensional stacked LSI (Large Scale integration) having a plurality of integrated circuit layers stacked together and electrically connected with interlayer via hole wiring.